MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 587
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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22.14.3.5 CPU Address, Attributes (ADDR, ATTR)
22.14.3.6 CPU Status (PSTAT)
22.14.3.7 OnCE Debug Output (DEBUG)
22.14.4 OnCE Controller Registers
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
The CPU address and attribute information may be used in the memory
breakpoint logic to qualify memory breakpoints with access address and
cycle type information.
The trace logic uses the PSTAT signals to qualify trace count
decrements with specific CPU activity.
The DEBUG signal is used to indicate to on-chip resources that a debug
session is in progress. Peripherals and other units may use this signal to
modify normal operation for the duration of a debug session. This may
involve the CPU executing a sequence of instructions solely for the
purpose of visibility/system control. These instructions are not part of the
normal instruction stream that the CPU would have executed had it not
been placed in debug mode.
This signal is asserted the first time the CPU enters the debug state and
remains asserted until the CPU is released by a write to the OnCE
Command Register with the GO and EX bits set, and a register specified
as either no register selected or the CPUSCR. This signal remains
asserted even though the CPU may enter and exit the debug state for
each instruction executed under control of the OnCE controller.
This section describes the OnCE controller registers:
All OnCE registers are addressed by means of the RS field in the OCMR,
as shown in
•
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
OnCE Command Register (OCMR)
OnCE Control Register (OCR)
OnCE Status Register (OSR)
JTAG Test Access Port and OnCE
Go to: www.freescale.com
Table
22-4.
JTAG Test Access Port and OnCE
Functional Description
Advance Information
587
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