MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 557
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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21.8 Interrupts
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
NOTE:
When no chip select pin is available, the active chip select can still
terminate the bus cycle. If both the CSEN and TAEN bits are 1 and the
address/options match the chip select configuration, then the chip select
logic asserts the internal termination signal; the bus cycle terminates
after the programmed number of wait states. If the external TA or TEA
pin is asserted before the chip select logic asserts the internal cycle
termination signal, then the bus cycle is terminated early.
If internal address bit 31 is 0, then the access is internal. If internal
address bit 31 is 1, then the access is external.
Chip select logic does not decode internal address bits A[30:25].
The chip select module does not generate interrupt requests.
Chip Select Block Size
1. The chip selects do not decode A[30:25]. Thus, the total 32-Mbyte block size is repeat-
2. If the EMINT bit in the chip configuration module CCR is set, then CS1 matches only inter-
Freescale Semiconductor, Inc.
ed/mirrored in external memory space.
nal accesses to the 8-MB block starting at address 0 to support emulation of internal mem-
ory. Thus, A[31:23] match 0xxx_xxx0_0.
CS0
CS1
CS2
CS3
For More Information On This Product,
Table 21-4. Chip Select Address Range Encoding
Go to: www.freescale.com
8 MB
8 MB
8 MB
8 MB
Chip Select Module
0x8000_0000–0x807f_ffff
0x8100_0000–0x817f_ffff
0x8080_0000–0x80ff_ffff
0x8180_0000–0x81ff_ffff
Address Range
Address Bits Compared
1xxx_xxx0_1
1xxx_xxx0_0
1xxx_xxx1_0
1xxx_xxx1_1
(A[31:23])
Advance Information
Chip Select Module
(1)
Interrupts
(2)
557
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