MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 455
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
NOTE:
If a set CCW pause bit is encountered in either externally gated mode,
the pause flag will not set, and execution continues without pausing. This
has allowed for the modified behavior of PF1 in the externally gated
modes.
CF2 — Queue 2 Completion Flag
used to determine if queue 1 should be enabled again. In either
externally gated mode, setting PF1 indicates that the results for
queue 1 have not been collected during one scan (coherently).
PF1 is maintained by the QADC regardless of whether the
corresponding interrupt is enabled. PF1 may be polled to determine if
the QADC has reached a pause in scanning a queue.
See
modes.
CF2 indicates that a queue 2 scan has been completed. CF2 is set by
the QADC when the input channel sample requested by the last CCW
in queue 2 is converted, and the result is stored in the result table.
The end-of-queue 2 is identified when the current CCW contains
an end-of-queue code (channel 63) instead of a valid channel number
Freescale Semiconductor, Inc.
Externally triggered single-scan
Externally triggered continuous-scan
Interval timer trigger single-scan
Interval timer continuous-scan
Software-initiated single-scan
Software-initiated continuous-scan
Externally gated single-scan
Externally gated continuous-scan
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
1 = Queue 1 has reached a pause or gate closed before
0 = Queue 1 has not reached a pause or gate has not closed before
Table 19-6
end-of-queue in gated mode.
end-of-queue in gated mode.
Go to: www.freescale.com
Scan Mode
Table 19-6. CCW Pause Bit Response
for a summary of CCW pause bit response in all scan
Queued Analog-to-Digital Converter (QADC)
Queue Operation
Continues
Continues
Continues
Continues
Pauses
Pauses
Pauses
Pauses
Register Descriptions
Advance Information
PF Asserts?
Yes
Yes
Yes
Yes
Yes
Yes
No
No
455
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