MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 418

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Serial Peripheral Interface Module (SPI)
Advance Information
418
Legend:
BEGIN TRANSMISSION
CHANGE OUTPUT
CHANGE OUTPUT
SS PIN OUTPUT
t
t
t
t
MSB FIRST (LSBFE = 0):
LSB FIRST (LSBFE = 1):
SCK (CPOL = 0)
SCK (CPOL = 1)
L
T
I
L
SAMPLE INPUT
MASTER ONLY
, t
SLAVE SS PIN
= Minimum idling time between transmissions (minimum SS high time)
= Minimum leading time before the first SCK edge
= Minimum trailing time after the last SCK edge
T
, and t
MOSI/MISO
MOSI PIN
MISO PIN
I
are guaranteed for master mode and required for slave mode.
Figure 18-12. SPI Clock Format 0 (CPHA = 0)
After the 16th and final SCK edge:
Figure 18-12
The SS pin of the master must be either high or configured as a
general-purpose output not affecting the SPI.
When CPHA = 0, the slave SS pin must be negated and reasserted
between bytes.
t
L
MSB
LSB
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
Data that was in the master SPIDR is in the slave SPIDR. Data
that was in the slave SPIDR is in the master SPIDR.
The SCK clock stops and the SPIF flag in SPISR is set, indicating
that the transmission is complete. If the SPIE bit in SPCR1 is set,
SPIF generates an interrupt request.
Serial Peripheral Interface Module (SPI)
Bit 6
Bit 1
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shows the timing of a transmission with the CPHA bit clear.
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
Bit 2
Bit 5
END TRANSMISSION
Bit 1
Bit 6
MSB
LSB
MINIMUM 1/2 SCK
t
T
FOR t
t
I
T
, t
MOTOROLA
L
t
, t
L
l