MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 59

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
P = Current pin state
0x00c0_0011
0x00c0_0012
0x00c0_0013
0x00c0_0014
0x00c0_0015
0x00c0_0017
0x00c0_0018
0x00c0_0019
0x00c0_001a
Address
Port G Data Direction
Port H Data Direction
Port F Data Direction
Register Name
Port I Data Direction
Port C Pin Data/Set
Port A Pin Data/Set
Port B Pin Data/Set
U = Unaffected
(PORTCP/SETC)
Register (DDRG)
(PORTAP/SETA)
(PORTBP/SETB)
Register (DDRH)
Register (DDRF)
Register (DDRI)
See page 276.
See page 276.
See page 276.
See page 276.
See page 277.
See page 277.
See page 277.
Data Register
Data Register
Data Register
Reserved
Figure 2-4. Register Summary (Sheet 3 of 37)
Freescale Semiconductor, Inc.
For More Information On This Product,
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read: PORTAP7 PORTAP6 PORTAP5 PORTAP4 PORTAP3 PORTAP2 PORTAP1 PORTAP0
Read: PORTBP7 PORTBP6 PORTBP5 PORTBP4 PORTBP3 PORTBP2 PORTBP1 PORTBP0
Read: PORTCP7 PORTCP6 PORTCP5 PORTCP4 PORTCP3 PORTCP2 PORTCP1 PORTCP0
Write:
Write:
Write:
Write:
Write:
Write:
Write:
DDRG7
DDRH7
DDRF7
SETA7
SETB7
SETC7
DDRI7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
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0
0
0
0
P
P
P
System Memory Map
= Writes have no effect and the access terminates without a transfer error exception.
DDRG6
DDRF6
DDRH6
SETA6
SETB6
SETC6
DDRI6
Writes have no effect, reads return 0s, and the access terminates
P
P
P
6
0
6
0
6
0
6
0
6
6
6
6
DDRF5
DDRG5
DDRH5
SETC5
SETA5
SETB5
DDRI5
P
P
P
5
0
5
0
5
0
5
0
5
5
5
5
without a transfer error exception.
DDRG4
DDRH4
DDRF4
SETC4
SETA4
SETB4
DDRI4
4
0
4
0
4
0
4
0
4
4
P
4
P
4
P
Bit Number
DDRG3
DDRH3
DDRF3
SETA3
SETB3
SETC3
DDRI3
P
P
P
3
0
3
0
3
0
3
0
3
3
3
3
DDRG2
DDRF2
DDRH2
SETA2
SETB2
SETC2
DDRI2
P
P
P
2
0
2
0
2
0
2
0
2
2
2
2
System Memory Map
Advance Information
DDRG1
DDRH1
DDRF1
SETC1
SETA1
SETB1
DDRI1
1
0
1
0
1
0
1
0
1
1
P
1
P
1
P
Register Map
DDRG0
DDRH0
DDRF0
SETA0
SETB0
SETC0
DDRI0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
0
0
0
0
P
P
P
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