MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 416

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Serial Peripheral Interface Module (SPI)
18.8.3 Transmission Formats
18.8.3.1 Transfer Format When CPHA = 1
Advance Information
416
The CPHA and CPOL bits in SPICR1 select one of four combinations of
serial clock phase and polarity. Clock phase and polarity must be
identical for the master SPI device and the communicating slave device.
Some peripherals require the first SCK edge to occur before the slave
MSB becomes available at its MISO pin. When the CPHA bit is set, the
master SPI waits for a synchronization delay of one-half SCK clock
cycle. Then it issues the first SCK edge at the beginning of the
transmission. The first edge causes the slave to transmit its MSB to the
MISO pin of the master. The second edge and the following
even-numbered edges latch the data. The third edge and the following
odd-numbered edges shift the latched slave data into the master shift
register and shift master data out on the master MOSI pin.
After the 16th and final SCK edge:
Figure 18-11
The SS pin of the master must be either high or configured as a
general-purpose output not affecting the SPI.
When CPHA = 1, the slave SS line can remain low between bytes. This
format is good for systems with a single master and a single slave driving
the MISO data line.
Writing to SPIDR while a transmission is in progress sets the WCOL flag
to indicate a write collision and inhibits the write. WCOL does not
generate an interrupt request; the SPIF interrupt request comes at the
end of the transfer that was in progress at the time of the error.
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Data that was in the master SPIDR register is in the slave SPIDR.
Data that was in the slave SPIDR register is in the master SPIDR.
The SCK clock stops and the SPIF flag in SPISR is set, indicating
that the transmission is complete. If the SPIE bit in SPCR1 is set,
SPIF generates an interrupt request.
Serial Peripheral Interface Module (SPI)
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shows the timing of a transmission with the CPHA bit set.
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
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