MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 351

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MMC2114CFCAG33

Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheets

Specifications of MMC2114CFCAG33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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16.9 Reset
16.10 Interrupts
16.10.1 Timer Channel Interrupts (CxF)
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
NOTE:
Reset initializes the timer registers to a known startup state as described
in
Table 16-8
A channel flag is set when an input capture or output compare event
occurs. Clear a channel flag by writing a 1 to the flag.
When the fast flag clear all bit, TFFCA, is set, an input capture read or
an output compare write clears the corresponding channel flag. TFFCA
is in Timer System Control Register 1 (TIMSCR1).
When a channel flag is set, it does not inhibit subsequent output
compares or input captures
16.7 Memory Map and
Freescale Semiconductor, Inc.
For More Information On This Product,
Channel 3 IC/OC
Channel 2 IC/OC
Channel 1 IC/OC
Channel 0 IC/OC
PA overflow
PA input
Timer overflow
Interrupt Request
Timer Modules (TIM1 and TIM2)
lists the interrupt requests generated by the timer.
Go to: www.freescale.com
Table 16-8. Timer Interrupt Requests
Registers.
PAOVF
PAIF
Flag
TOF
C3F
C2F
C1F
C0F
Timer Modules (TIM1 and TIM2)
Enable Bit
PAOVI
TOI
C3I
C2I
C1I
C0I
PAI
Advance Information
Reset
351

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