MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 417

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

18.8.3.2 Transfer Format When CPHA = 0
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
BEGIN TRANSMISSION
Legend:
CHANGE OUTPUT
CHANGE OUTPUT
SS PIN OUTPUT
MSB FIRST (LSBFE = 0):
LSB FIRST (LSBFE = 1):
t
t
t
t
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE INPUT
MASTER ONLY
L
T
I
L
SLAVE SS PIN
= Minimum idling time between transmissions (minimum SS high time)
, t
= Minimum leading time before the first SCK edge
= Minimum trailing time after the last SCK edge
T
MOSI/MISO
, and t
MOSI PIN
MISO PIN
I
are guaranteed for master mode and required for slave mode.
t
L
Figure 18-11. SPI Clock Format 1 (CPHA = 1)
In some peripherals, the slave MSB is available at its MISO pin as soon
as the slave is selected. When the CPHA bit is clear, the master SPI
delays its first SCK edge for half a SCK cycle after the transmission
starts. The first edge and all following odd-numbered edges latch the
slave data. Even-numbered SCK edges shift slave data into the master
shift register and shift master data out on the master MOSI pin.
MSB
LSB
Freescale Semiconductor, Inc.
For More Information On This Product,
Serial Peripheral Interface Module (SPI)
BIT 6
BIT 1
Go to: www.freescale.com
BIT 5
BIT 2
BIT 4
BIT 3
BIT 3
BIT 4
BIT 2
BIT 5
END TRANSMISSION
Serial Peripheral Interface Module (SPI)
BIT 1
BIT 6
MSB
LSB
t
T
Functional Description
MINIMUM 1/2 SCK
Advance Information
t
I
FOR t
t
L
T
, t
L
, t
l
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