MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 601

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.14.9.2 Debug Request During Normal Activity
22.14.9.3 Debug Request During Stop, Doze, or Wait Mode
22.14.9.4 Software Request During Normal Activity
22.14.10 Enabling OnCE Trace Mode
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
NOTE:
vector and the first instruction of the reset exception handler but does not
execute an instruction before entering debug mode.
Setting the DR bit in the OCR during normal device activity causes the
device to finish the execution of the current instruction and then enter
debug mode. Note that in this case the device completes the execution
of the current instruction and stops after the newly fetched instruction
enters the CPU instruction latch. This process is the same for any newly
fetched instruction, including instructions fetched by interrupt processing
or those that will be aborted by interrupt processing.
Setting the DR bit in the OCR when the device is in stop, doze, or wait
mode (for instance, after execution of a STOP, DOZE, or WAIT
instruction) causes the device to exit the low-power state and enter the
debug mode. Note that in this case, the device completes the execution
of the STOP, DOZE, or WAIT instruction and halts after the next
instruction enters the instruction latch.
Executing the BKPT instruction when the FDB (force debug enable
mode) control bit in the Control State Register is set causes the CPU to
enter debug mode after the instruction following the BKPT instruction
has entered the instruction latch.
When the OnCE trace mode mechanism is enabled and the trace count
is greater than zero, the trace counter is decremented for each
instruction executed. Completing execution of an instruction when the
trace counter is zero causes the CPU to enter debug mode.
Only instructions actually executed cause the trace counter to
decrement. An aborted instruction does not decrement the trace counter
and does not invoke debug mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
JTAG Test Access Port and OnCE
Go to: www.freescale.com
JTAG Test Access Port and OnCE
Functional Description
Advance Information
601