MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 479
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
The pause feature can be used to divide queue 1 and/or queue 2 into
multiple subqueues. A subqueue is defined by setting the pause bit in
the last CCW of the subqueue.
Figure 19-22
create subqueues. Queue 1 is shown with four CCWs in each subqueue
and queue 2 has two CCWs in each subqueue.
The operating mode selected for queue 1 determines what type of
trigger event causes the execution of each of the subqueues within
queue 1. Similarly, the operating mode for queue 2 determines the type
of trigger event required to execute each of the subqueues within
queue 2.
For example, when the external trigger rising edge continuous-scan
mode is selected for queue 1, and there are six subqueues within
queue 1, a separate rising edge is required on the external trigger pin
after every pause to begin the execution of each subqueue (refer to
Figure
The choice of single-scan or continuous-scan applies to the full queue,
and is not applied to each subqueue. Once a subqueue is initiated, each
CCW is executed sequentially until the last CCW in the subqueue is
executed and the pause state is entered. Execution can only continue
with the next CCW, which is the beginning of the next subqueue. A
subqueue cannot be executed a second time before the overall queue
execution has been completed.
•
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
When queue 2 is active and a trigger event occurs for queue 1, the
current queue 2 conversion is aborted. The status register reports
the queue 2 status as suspended. Any trigger events occurring for
queue 2 while it is suspended are flagged as trigger overruns.
Once queue 1 reaches the completion or the paused state, queue
2 begins executing again. The programming of the RESUME bit in
QACR2 determines which CCW is executed in queue 2.
When simultaneous trigger events occur for queue 1 and queue 2,
queue 1 begins execution and the queue 2 status is changed to
trigger pending.
When subqueues are paused
19-22).
Go to: www.freescale.com
shows the CCW format and an example of using pause to
Queued Analog-to-Digital Converter (QADC)
Advance Information
Digital Control
479
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