MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 524

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MMC2114CFCAG33

Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheets

Specifications of MMC2114CFCAG33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Queued Analog-to-Digital Converter (QADC)
19.12 Interrupts
19.12.1 Interrupt Operation
Advance Information
524
CAUTION:
Leakage below 200 nA is obtainable only within a limited temperature
range.
The four interrupt lines are outputs of the module and have no priority or
arbitration within the module.
QADC inputs can be monitored by polling or by using interrupts. When
interrupts are not needed, the completion flag and the pause flag for
each queue can be monitored in the Status Register (QASR0). In other
words, flag bits can be polled to determine when new results are
available.
Table 19-16
correspond to queue 1 and queue 2 activity.
Queue 1
Queue 2
Queue
Source Impedance
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Table 19-16. QADC Status Flags and Interrupt Sources
Table 19-15. Error Resulting from Input Leakage (I
100 k
10 k
1 k
Result written for last CCW in queue 1
Result written for a CCW with pause bit set in
Result written for last CCW in queue 2
Result written for a CCW with pause bit set in
queue 1
queue 2
Go to: www.freescale.com
shows the status flag and interrupt enable bits which
0.2 counts
Queue Activity
2 counts
100 nA
Leakage Value (10-Bit Conversions)
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
0.4 counts
200 nA
4 count
0.1 counts
10 counts
1 counts
500 nA
Status
Flag
CF1
CF2
PF1
PF2
MOTOROLA
Off
0.2 counts
20 counts
Enable Bit
1000 nA
2 counts
Interrupt
)
CIE1
CIE2
PIE1
PIE2

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