MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 167
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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7.4 Microarchitecture Summary
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
DATA CALCULATION
WRITEBACK BUS
SIGN EXT.
GENERAL-PURPOSE
REGISTER FILE
X PORT
32 BITS X 16
ADDER/LOGICAL PRIORITY ENCODER/
MUX
ZERO DETECT RESULT MUX
BARREL SHIFTER
REGISTER FILE
Figure 7-1. M•CORE Processor Block Diagram
ALTERNATE
32 BITS X 16
MULTIPLIER
Figure 7-1
The processor utilizes a 4-stage pipeline for instruction execution. The
instruction fetch, instruction decode/register file read, execute, and
register file writeback stages operate in an overlapped fashion, allowing
single clock instruction execution for most instructions.
The execution unit consists of a 32-bit arithmetic/logic unit (ALU), a
32-bit barrel shifter, a find-first-one unit, result feed-forward hardware,
support hardware for multiplication and division, and multiple-register
load and store instructions.
DIVIDER
Freescale Semiconductor, Inc.
M•CORE M210 Central Processor Unit (CPU)
For More Information On This Product,
H/W ACCELERATOR INTERFACE BUS
Y PORT
is a block diagram of the M•CORE processor.
MUX
REGISTER FILE
Go to: www.freescale.com
SCALE
32 BITS X 13
CONTROL
IMMEDIATE
MUX
DATA
BUS
M•CORE M210 Central Processor Unit (CPU)
INCREMENT
ADDRESS GENERATION
INSTRUCTION PIPELINE
INSTRUCTION DECODE
PC
ADDRESS MUX
Microarchitecture Summary
BRANCH
ADDER
Advance Information
ADDRESS
BUS
167
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