MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 437

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.8 Register Descriptions
19.8.1 QADC Module Configuration Register (QADCMCR)
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Address: 0x00ca_0000 and 0x00ca_0001
Reset:
Reset:
Read:
Read:
Write:
Write:
Figure 19-3. QADC Module Configuration Register (QADCMCR)
This subsection describes the QADC registers.
QADCMCR contains bits that control QADC debug and stop modes and
determines the privilege level required to access most registers.
QSTOP — Stop Enable Bit
QDBG — Debug Enable Bit
SUPV — Supervisor/Unrestricted Data Space Bit
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
QSTOP
1 = Force QADC to idle state.
0 = QADC operates normally.
1 = Finish any conversion in progress, then freeze in debug mode
0 = QADC operates normally.
1 = All QADC registers are accessible in supervisor mode only;
0 = Only QADCMCR and QADCTEST require supervisor mode
SUPV
Bit 15
Bit 7
0
1
user mode accesses have no effect and result in a cycle
termination error.
access; access to all other QADC registers is unrestricted
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= Writes have no effect and the access terminates without a transfer error exception.
QDBG
14
0
6
0
0
13
0
0
5
0
0
12
0
0
4
0
0
Queued Analog-to-Digital Converter (QADC)
11
0
0
3
0
0
10
0
0
2
0
0
Register Descriptions
Advance Information
9
0
0
1
0
0
Bit 8
Bit 0
0
0
0
0
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