MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 445
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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19.8.5.2 QADC Control Register 1 (QACR1)
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Address: 0x00ca_000c and 0x00ca_000d
Reset:
Reset:
Read:
Read:
Write:
Write:
QADC Control Register 1 (QACR1) is the mode control register for
queue 1. This register governs queue operating mode and the use of
completion and/or pause interrupts. Typically, these bits are written once
when the QADC is initialized and not changed thereafter.
Stop mode resets this register ($0000).
Read: Anytime
Write: Anytime except during stop mode
CIE1 — Queue 1 Completion Interrupt Enable Bit
CIE1 enables an interrupt request upon completion of queue 1. The
interrupt request is initiated when the conversion is complete for the
last CCW in queue 1.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
1 = Enable queue 1 completion interrupt.
0 = Disable queue 1 completion interrupt.
Bit 15
CIE1
Bit 7
0
0
0
Figure 19-9. QADC Control Register 1 (QACR1)
Go to: www.freescale.com
= Writes have no effect and the access terminates without a transfer error exception.
PIE1
14
0
6
0
0
SSE1
13
0
0
5
0
0
MQ112
12
0
4
0
0
Queued Analog-to-Digital Converter (QADC)
MQ111
11
0
3
0
0
MQ110
10
0
2
0
0
Register Descriptions
Advance Information
MQ19
9
0
1
0
0
MQ18
Bit 8
Bit 0
0
0
0
445
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