MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 456
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
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Queued Analog-to-Digital Converter (QADC)
Advance Information
456
PF2 — Queue 2 Pause Flag
or when the currently completed CCW is in the last location of the
CCW RAM.
When CF2 is set and queue 2 completion interrupts are enabled
(CIE2 = 1), the QADC requests an interrupt. The interrupt request is
cleared when a 0 is written to the CF2 bit after it has been read as a
1. Once set, CF2 can be cleared only by a reset or by writing a 0 to it.
CF2 is updated by the QADC regardless of whether the
corresponding interrupt is enabled. This allows polled recognition of
queue 2 scan completion.
PF2 indicates that a queue 2 scan has reached a pause. PF2 is set
by the QADC when the current queue 2 CCW has the pause bit set,
the selected input channel has been converted, and the result has
been stored in the result table.
Once PF2 is set, the queue enters the paused state and waits for a
trigger event to allow queue execution to continue. However, a
special case occurs when the CCW with the pause bit set is the last
CCW in a queue: Queue execution is complete. The queue status
becomes idle, not paused, and both the pause and completion flags
are set.
Another special case occurs when queue 2 is operating in
software-initiated single-scan or continuous-scan mode and a CCW
pause bit is set. The QADC will set PF2 and will also automatically
generate a retrigger event that restarts execution after two QCLK
cycles. Pause mode is never entered.
When PF2 is set and interrupts are enabled (PIE2 = 1), the QADC
requests an interrupt. The interrupt request is cleared when a 0 is
written to PF2, after it has been read as a 1. Once set, PF2 can be
cleared only by a reset or by writing a 0 to it.
PF2 is maintained by the QADC regardless of whether the
corresponding interrupt is enabled. PF2 may be polled to determine if
the QADC has reached a pause in scanning a queue.
See
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
1 = Queue 2 has reached a pause.
0 = Queue 2 has not reached a pause.
Table 19-6
Go to: www.freescale.com
for a summary of pause response in all scan modes.
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
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