MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 195
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
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Part Number:
MMC2114CFCAG33
Manufacturer:
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8.8.4 Interrupt Configuration
8.8.4.1 CPU Configuration
8.8.4.2 Interrupt Controller Configuration
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
NOTE:
After reset, all interrupts are disabled by default. To properly configure
the system to handle interrupt requests, configuration must be
performed at three levels:
Configure the CPU first, the interrupt controller second, and the local
interrupt sources last.
For fast interrupts, set the FIE[x] bit in FIER in the CPU. For normal
interrupts, set the NIE[x] bit. Both FIE and NIE are cleared at reset.
To allow long latency, multicycle instructions to be interrupted before
completion, set the IC bit in the PSR.
VBR in the CPU defines the base address of the exception vector table.
If autovectors are to be used, then initialize the INT and FINT
autovectors (vector numbers 10 and 11, respectively). If vectored
interrupts are to be used, then initialize the vectored interrupts (vector
numbers 32–63 and/or 64–95). Whether 32 or 64 vectors are required
depends on whether the fast interrupts share vectors with the normal
interrupt sources based on the FVE bit in the interrupt controller ICR.
For each vector number, create an interrupt service routine to service
the interrupt, clear the local interrupt flag, and return from the interrupt
routine.
By default, each interrupt source to the interrupt controller is assigned a
priority level of 0 and disabled. Each interrupt source can be
programmed to one of 32 priority levels and enabled as either a fast or
normal interrupt source. Also, the FVE and AE bits in ICR can be
programmed to select autovectored/vectored interrupts and also
•
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
CPU
Interrupt controller
Local interrupt sources
Go to: www.freescale.com
Interrupt Controller Module
Interrupt Controller Module
Functional Description
Advance Information
195
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