MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 434

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Queued Analog-to-Digital Converter (QADC)
19.6.3 External Trigger Input Pins
19.6.4 Multiplexed Address Output Pins
Advance Information
434
Each port QB pin is configured as an input or output by programming the
Port Data Direction Register (DDRQB). The digital input signal states are
read from the port QB Data Register (PORTQB) when DDRQB specifies
that the pins are inputs. The digital data in PORTQB is driven onto the
port QB pins when the corresponding bits in DDRQB specify output.
See
DDRQB).
The QADC has two external trigger pins, ETRIG2 and ETRIG1. Each
external trigger input is associated with one of the scan queues, queue
1 or queue 2. The assignment of ETRIG[2:1] to a queue is made by the
TRG bit in QADC Control Register 0 (QACR0). When TRG = 0, ETRIG1
triggers queue 1 and ETRIG2 triggers queue 2. When TRG = 1, ETRIG1
triggers queue 2 and ETRIG2 triggers queue 1. See
Registers.
In non-multiplexed mode, the QADC analog input pins are connected to
an internal multiplexer which routes the analog signals into the internal
A/D converter.
In externally multiplexed mode, the QADC allows automatic channel
selection through up to four external 4-to-1 multiplexer chips. The QADC
provides a 2-bit multiplexed address output to the external multiplexer
chips to allow selection of one of four inputs. The multiplexed address
output signals, MA1 and MA0, can be used as multiplexed address
output bits or as general-purpose I/O when external multiplexed mode is
not being used.
MA[1:0] are used as the address inputs for up to four 4-channel
multiplexer chips. Because the MA[1:0] pins are digital outputs in
multiplexed mode, the state of their corresponding data direction bits in
DDRQA is ignored.
Freescale Semiconductor, Inc.
19.8.4 Port QA and QB Data Direction Register (DDRQA and
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Go to: www.freescale.com
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
19.8.5 Control
MOTOROLA