MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 592

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

JTAG Test Access Port and OnCE
Advance Information
592
IDRE — Internal Debug Request Enable Bit
TME — Trace Mode Enable Bit
FRZC — Freeze Control Bit
RCB and RCA — Memory Breakpoint B and A Range Control Bits
BCB4–BCB0 and BCA4–BCA0 — Memory Breakpoint B and A Control
Fields
The internal debug request (IDR) input to the OnCE control logic may
not be used in all implementations. In some implementations, the IDR
control input may be connected and used as an additional hardware
debug request. Test logic reset clears the IDRE bit.
TME enables trace operation. Test logic reset clears the TME bit.
Trace operation is also affected by the SQC field.
This control bit is used in conjunction with memory breakpoint B
registers to select between asserting a breakpoint condition when a
memory breakpoint B occurs or freezing the PC FIFO from further
updates when memory breakpoint B occurs while allowing the CPU to
continue execution. The PC FIFO remains frozen until the FRZO bit
in the OSR is cleared.
RCB and RDA condition enabled memory breakpoint occurrences
happen when memory breakpoint matches are either within or outside
the range defined by memory base address and mask.
The BCB and BCA fields enable memory breakpoints and qualify the
access attributes to select whether the breakpoint matches are
recognized for read, write, or instruction fetch (program space)
accesses. Test logic reset clears BCB4–BCB0 and BCA4–BCA0.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = IDR input enabled
0 = IDR input disabled
1 = Trace operation enabled
0 = Trace operation disabled
1 = Memory breakpoint B occurrence freezes PC FIFO and does
0 = Memory breakpoint B occurrence asserts breakpoint condition.
1 = Condition breakpoint on access outside of range
0 = Condition breakpoint on access within range
JTAG Test Access Port and OnCE
not assert breakpoint condition.
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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
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