MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 556
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chip Select Module
21.7 Functional Description
Advance Information
556
NOTE:
CSEN — Chip Select Enable Bit
Each chip select can provide a chip enable signal for an external device
and assert the internal bus cycle termination signal.
Setting the CSEN bit in CSCR enables the chip select to provide an
external chip enable signal.
Setting both the CSEN and TAEN bits in CSCR enables the chip select
to generate the internal bus cycle termination signal.
Both the chip select pin assertion and the bus cycle termination function
depend on an initial address/option match for activation. During the
matching process, the fixed base address of each chip select is
compared to the corresponding address for the bus cycle to determine
whether an address match has occurred. This match is further qualified
by comparing the internal read/write indication and access type with the
programmed values in CSCR of each chip select. When the address and
option information match the current cycle, the chip select is activated. If
no chip select matches the bus cycle information for the current access,
the chip select logic does not respond in any way.
Only one chip select can be active for a given bus cycle. The
configuration of the active chip select, determined by the wait state
(WS/WWS) field, the port size (PS) field, and the write enable (WE) field,
is used for the access.
WWS and WS are valid only if the TAEN bit is 1 for the active chip select.
logic can still terminate the access before the internal cycle
termination signal is asserted by asserting the external TA pin.
The CSEN bit enables the chip select logic. When the chip select
function is disabled, the CSx signal is negated high.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Internal cycle termination signal asserted by chip select logic
0 = Internal cycle termination signal asserted by external logic
1 = Chip select function enabled
0 = Chip select function disabled
Go to: www.freescale.com
Chip Select Module
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
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