MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 555
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
WS[2:0] — Wait States Field
TAEN — Transfer Acknowledge Enable Bit
The WS field determines the number of wait states for the chip select
logic to insert before asserting the internal cycle termination signal.
One wait state is equal to one system clock cycle. If WS is configured
for zero wait states, then the internal cycle termination signal is
asserted in the clock cycle following the start of the cycle access,
resulting in one-clock transfers. A WS configured for one wait state
means that the internal cycle termination signal is asserted two clock
cycles after the start of the cycle access.
Since the internal cycle termination signal is asserted internally after
the programmed number of wait states, software can adjust the bus
timing to accommodate the access speed of the external device. With
up to seven possible wait states, even slow devices can be interfaced
with the MCU.
The TAEN bit determines whether the internal cycle termination
signal is asserted by the chip select logic when accesses occur to the
address range defined by the corresponding chip select. When TAEN
is 0, an external device is responsible for asserting the external TA pin
to terminate the bus access. When TAEN is 1, the chip select logic
asserts the internal cycle termination signal after a time determined
by the programmed number of wait states. When TAEN is 1, external
Freescale Semiconductor, Inc.
WS[2:0]
For More Information On This Product,
000
001
010
011
100
101
110
111
Table 21-3. Chip Select Wait States Encoding
Go to: www.freescale.com
Read Access
Chip Select Module
0
1
2
3
4
5
6
7
WWS = 0
Write Access
Number of Wait States
0
1
2
3
4
5
6
7
Read Access
0
1
2
3
4
5
6
7
Memory Map and Registers
WWS = 1
Advance Information
Chip Select Module
Write Access
1
2
3
4
5
6
7
8
555
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