MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 207
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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10.6 Block Diagram
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
The SGFM module shown in
blocks, the M•CORE local bus (MLB) and IP bus interfaces, FLASH
interface, register blocks, and the BIST engine.
Each 64-Kbyte FLASH physical block is arranged as 32,768 halfwords
(16 bits) and may be read as either bytes or aligned halfwords. Aligned
word access is provided by concatenating the outputs of two FLASH
physical blocks. Reads of bytes, aligned halfwords, and aligned words
require one clock cycle. Misaligned read accesses are not supported
and will result in a cycle termination transfer error.
All FLASH program, erase, and verify commands operate on adjacent
FLASH physical blocks and are initiated with a single aligned 32-bit write
to the appropriate array location. Any other write operation will cause a
cycle termination transfer error. For erase purposes, a FLASH physical
block is organized as 1024 rows of 64 bytes with a single erase page
consisting of 8 rows (512 bytes). Page erase operates simultaneously on
two interleaving erase pages in adjacent FLASH physical blocks, making
the minimum effective erase size 1 Kbyte. Mass erase operates
simultaneously on two adjacent FLASH physical blocks in their entirety
and erases a total of 128 Kbytes of array space.
Each pair of FLASH physical blocks requires a banked set of registers to
control program and erase operations.
module configured with four sets of banked registers. A 128 K-byte
module would only require one set, a 256-Kbyte module would require
two sets and a 384-Kbyte module would require three sets of banked
registers.
An erased FLASH bit reads 1 and a programmed FLASH bit reads 0.
The SGFM features a sense amplifier timeout block that automatically
reduces current consumption during reads at low clock frequencies.
Freescale Semiconductor, Inc.
Second Generation FLASH for M•CORE (SGFM)
For More Information On This Product,
Go to: www.freescale.com
Figure 10-1
Second Generation FLASH for M•CORE (SGFM)
Figure 10-1
contains the FLASH physical
shows a 512-Kbyte
Advance Information
Block Diagram
207
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