MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 390
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Serial Communications Interface Modules (SCI1 and SCI2)
17.12.6 Receiver Wakeup
17.12.6.1 Idle Input Line Wakeup (WAKE = 0)
Advance Information
390
Serial Communications Interface Modules (SCI1 and SCI2)
So that the SCI can ignore transmissions intended only for other devices
in multiple-receiver systems, the receiver can be put into a standby
state. Setting the RWU bit in SCICR2 puts the receiver into a standby
state during which receiver interrupts are disabled.
The transmitting device can address messages to selected receivers by
including addressing information in the initial frame or frames of each
message.
The WAKE bit in SCICR1 determines how the SCI is brought out of the
standby state to process an incoming message. The WAKE bit enables
either idle line wakeup or address mark wakeup.
When WAKE = 0, an idle condition on the RXD pin clears the RWU bit
and wakes up the receiver. The initial frame or frames of every message
contain addressing information. All receivers evaluate the addressing
information, and receivers for which the message is addressed process
the frames that follow. Any receiver for which a message is not
addressed can set its RWU bit and return to the standby state. The RWU
bit remains set and the receiver remains on standby until another idle
frame appears on the RXD pin.
Idle line wakeup requires that messages be separated by at least one
idle frame and that no message contains idle frames.
The idle frame that wakes up the receiver does not set the IDLE flag or
the RDRF flag.
The ILT bit in SCICR1 determines whether the receiver begins counting
logic 1s as idle frame bits after the start bit or after the stop bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
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