MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 213

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.7.1 Unbanked Register Descriptions
10.7.1.1 SGFM Configuration Register
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Address: 0x00d0_0000 and 0x00d0_0001
The unbanked registers are described in this subsection.
The SGFM Configuration Register (SGFMCR) is unbanked and is used
to configure and control the operation of the SGFM array and bus
interface unit (BIU).
FRZ — Freeze Enable Bit
EME — Emulation Enable Bit
Reset:
Reset:
Read:
Read:
Write:
Write:
Figure 10-3. SGFM Module Configuration Register (SGFMCR)
The FRZ bit is readable and writable in all modes. In debug mode the
SGFM behaves exactly as it does in user mode except that the LOCK
bit in SGFMCR and SGFMCLKD[6:0] bits are writable.
The EME bit is always readable and only writable when LOCK = 0.
EME places the SGFM in emulation mode, during which the SGFM
BIU will not assert TA or TEA to terminate read bus cycles of the
Freescale Semiconductor, Inc.
Second Generation FLASH for M•CORE (SGFM)
For More Information On This Product,
1 = Enter debug mode if debug signal on MLB is asserted
0 = Ignore debug mode if debug signal on MLB is asserted
Note 1. Reset state determined by chip reset configuration.
CBEIE
Bit 15
Bit 7
0
0
0
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= Reserved
CCIE
FRZ
14
0
6
0
KEYACC
13
0
0
5
0
Second Generation FLASH for M•CORE (SGFM)
Note 1
EME
12
4
0
0
11
0
0
3
0
0
LOCK
10
0
2
0
0
Module Memory Map
Advance Information
BKSEL1
9
0
0
1
0
BKSEL0
Bit 8
Bit 0
0
0
0
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