MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 135
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
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Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
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Part Number:
MMC2114CFCAG33
Manufacturer:
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4.8.2 Chip Mode Selection
4.8.3 Boot Device Selection
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
The chip mode is selected during reset and reflected in the MODE field
of the Chip Configuration Register (CCR). (See
Configuration
cannot be changed.
configuration.
During reset, certain module configurations depend on whether
emulation mode is active as determined by the state of the internal
emulation signal.
During reset configuration, the CS0 chip select pin is optionally
configured to select an external boot device. In this case, the CSEN bit
in CSCR0 is set, enabling CS0 after reset. CS0 will be asserted for the
initial boot fetch accessed from address 0x0. It is assumed that the reset
vector loaded from address 0x0 causes the CPU to start executing from
external memory space decoded by CS0. Also, the PS bit is configured
for either a 16-bit or 32-bit port size depending on the external boot
device. See
In emulation mode, the CS1 chip select pin is optionally configured for
emulating an internal memory. In emulation mode and booting from
internal memory, the CSEN bit in CSCR1 is set, enabling CS1 after
reset.
Master mode
Single-chip mode
FAST mode
Emulation mode
1. Modifying the default configurations is possible only if the external RCON pin is asserted.
Chip Configuration
Freescale Semiconductor, Inc.
For More Information On This Product,
Mode
Chip Configuration Module (CCM)
Table 4-8. Chip Configuration Mode Selection
Table
Go to: www.freescale.com
Register.) Once reset is exited, the operating mode
4-9.
Table 4-8
D26 driven high
D26 driven high
D26 driven high
D26 driven low
MODE2
shows the mode selection during reset
CCR Register MODE Field
D17 driven high
D17 driven high
D17 driven low
D17 don’t care
MODE1
Chip Configuration Module (CCM)
4.7.3.1 Chip
Functional Description
Advance Information
D16 driven high
D16 driven low
D16 don’t care
D16 don’t care
(1)
MODE0
135
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