MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 626

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MMC2114CFCAG33

Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheets

Specifications of MMC2114CFCAG33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Preliminary Electrical Specifications
Advance Information
626
1. All AC timing is shown with respect to 50% V
2. Timing is not guaranteed during the clock cycle of mode and/or setup changes (for example, changing pin function between
3. A[22:0], TSIZ[1:0], CS[3:0] valid to R/W (write), OE, EB asserted (minimum) spec is 0 ns. This parameter is characterized
4. Write/show data high-Z to OE asserted (minimum) or from EB negated (write — maximum) spec is 0 ns. This parameter is
5. To prevent an unintentional assertion glitch of the EB pins during a synchronous reset (and before the reset overrides
6. SHS high to show data or write data invalid (minimum) spec is 0 ns. This parameter is characterized before qualification
7. Write/show data high-Z and write/show data invalid is 0 ns for synchronous reset conditions.
8. t
No.
23
24
25
26
27
GPIO and primary function, changing GPIO between input/output functions, changing control registers that affect pin
functions).
before qualification rather than 100% tested.
characterized before qualification rather than 100% tested.
configure the chip in a stable mode), leave the port output data register bits associated with the EB GPO default of 1 and do
not pull the pins down with a current load.
rather than 100% tested.
maximum.
CLDOVS
CLKOUT high to data-out invalid write/show
Data-in valid to CLKOUT high read
CLKOUT high to data-in invalid read
TA, TEA asserted to CLKOUT high
CLKOUT high to TA, TEA negated
value reflects maximum specification for any bus cycle. For non-FLASH read cycles, t
Table 23-11. External Interface Timing Characteristics (Continued)
CLKOUT
Characteristic
(V
4
DD
Freescale Semiconductor, Inc.
For More Information On This Product,
= 2.7 V to 3.6 V, V
Figure 23-1. CLKOUT Timing
Preliminary Electrical Specifications
(1), (2)
Go to: www.freescale.com
DD
levels, unless otherwise noted.
(6), (7)
SS
5
= 0 V, T
2
Symbol
t
CHDOIW
t
t
t
t
DIVCH
CHDII
CHTN
TACH
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
1
A
= T
0.25 t
L
3
to T
Min
17
2
0
0
cyc
H
+ 9
)
CLDOVS
Max
is specified at 8 ns
MOTOROLA
Unit
ns
ns
ns
ns
ns

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