MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 589

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
EX — Exit Bit
RS4–RS0 — Register Select Field
bit has no effect. The processor leaves debug mode after the TAP
controller update-DR state is entered.
When the EX bit is set, the processor leaves debug mode and
resumes normal operation until another debug request is generated.
The exit command is executed only if the GO bit is set and the
operation is a read/write to the CPUSCR or a read/write to “no register
selected.” Otherwise, the EX bit has no effect. The processor exits
debug mode after the TAP controller update-DR state is entered.
The RS field defines the source for the read operation or the
destination for the write operation.
addresses.
Freescale Semiconductor, Inc.
RS4–RS0
00000
00001
00010
00011
00100
00101
00110
01000
01001
01010
01011
01100
01101
00111
01110
For More Information On This Product,
1 = Execute instruction in IR
0 = Inactive (no action taken)
1 = Leave debug mode
0 = Remain in debug mode
JTAG Test Access Port and OnCE
Go to: www.freescale.com
Table 22-4. OnCE Register Addressing
Reserved
Reserved
Reserved
OTC — OnCE trace counter
MBCA — memory breakpoint counter A
MBCB — memory breakpoint counter B
PC FIFO — program counter FIFO and increment counter
BABA — Breakpoint Address Base Register A
BABB — Breakpoint Address Base Register B
BAMA — Breakpoint Address Mask Register A
BAMB — Breakpoint Address Mask Register B
CPUSCR — CPU Scan Chain Register
Bypass — no register selected
OCR — OnCE Control Register
OSR — OnCE Status Register
Register Selected
Table 22-4
JTAG Test Access Port and OnCE
shows OnCE register
Functional Description
Advance Information
589