MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 564
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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JTAG Test Access Port and OnCE
22.3.1 Test Clock (TCLK)
22.3.2 Test Mode Select (TMS)
22.3.3 Test Data Input (TDI)
22.3.4 Test Data Output (TDO)
22.3.5 Test Reset (TRST)
22.3.6 Debug Event (DE)
Advance Information
564
TCLK is a test clock input to synchronize the test logic. TCLK is
independent of the processor clock. It includes an internal pullup
resistor.
TMS is a test mode select input (with an internal pullup resistor) that is
sampled on the rising edge of TCLK to sequence the TAP controller’s
state machine.
TDI is a serial test data input (with an internal pullup resistor) that is
sampled on the rising edge of TCLK.
TDO is a three-state test data output that is actively driven in the shift-IR
and shift-DR controller states. TDO changes on the falling edge of
TCLK.
TRST is an active low asynchronous reset with an internal pullup resistor
that forces the TAP controller into the test-logic-reset state.
This is a bidirectional, active-low signal.
As an output, this signal will be asserted for three system clocks,
synchronous to the rising CLKOUT edge, to acknowledge that the CPU
has entered debug mode as a result of a debug request or a breakpoint
condition.
Freescale Semiconductor, Inc.
For More Information On This Product,
JTAG Test Access Port and OnCE
Go to: www.freescale.com
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
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