MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 231
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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10.8.3 Program and Erase Operations
10.8.3.1 Setting the SGFMCLKD Register
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Read and write operations are both used for the program and erase
algorithms described in this subsection. These algorithms are controlled
by a state machine whose timebase is derived from the SGFM module
clock via a programmable counter.
The command register and associated address and data buffers operate
as a two stage FIFO so that a new command along with the necessary
address and data can be stored while the previous command is still in
progress. This pipelining speeds when programming more than one
word on a specific row, as the charge pumps can be kept on in between
two programming commands, thus saving the overhead needed to setup
the charge pumps. Buffer empty and command completion are indicated
by flags in the SGFM User Status Register. Interrupts will be requested
if enabled.
Prior to issuing any program or erase commands, SGFMCLKD must be
written to set the FLASH state machine clock (FCLK). The SGFM
module runs at the system clock frequency, but FCLK must be divided
down from the system clock to a frequency between 150 kHz and
200 kHz. Use the following procedure to set the PRDIV8 and DIV[5:0]
bits in SGFMCLKD:
1. If f
2. Determine DIV[5:0] by using the following equation. Keep only the
3. Thus the FLASH state machine clock will be:
Freescale Semiconductor, Inc.
Second Generation FLASH for M•CORE (SGFM)
For More Information On This Product,
PRDIV8 = 0.
integer portion of the result and discard any fraction. Do not round
the result.
SYS
Go to: www.freescale.com
is greater than 12.8 MHz, PRDIV8 = 1, otherwise
DIV[5:0] =
FCLK =
Second Generation FLASH for M•CORE (SGFM)
1 + (PRDIV8 x 7)
1 + (PRDIV8 x 7)
DIV[5:0] + 1
200 kHz
f
SYS
f
SYS
Advance Information
SGFM User Mode
231
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