MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 216

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Second Generation FLASH for M•CORE (SGFM)
10.7.1.3 SGFM Test Register
Advance Information
216
NOTE:
Address: 0x00d0_0004
DIVLD — Clock Divider Loaded Bit
PRDIV8 — Enable Prescaler Divide by 8 Bit
DIV[5:0] — Clock Divider Field
SGFMCLKD must be written with an appropriate value before
programming or erasing the FLASH array. Refer to
SGFMCLKD
The SGFM Test Register (SGFMTST) is unbanked and is used only for
factory testing.
Accesses to SGFMTST when not in test mode will result in a cycle
termination transfer error.
Reset:
Read:
Write:
The combination of PRDIV8 and DIV[5:0] effectively divides the
SGFM input clock down to a frequency between 150 kHz and
200 kHz. The frequency range of the SGFM clock is 150 kHz to
102.4 MHz.
Freescale Semiconductor, Inc.
Second Generation FLASH for M•CORE (SGFM)
For More Information On This Product,
1 = SGFMCLKD has been written since the last reset.
0 = SGFMCLKD has not been written.
1 = Enables a prescaler that divides the SGFM clock by 8 before it
0 = The SGFM clock is fed directly into the SGFMCLKD divider.
RSVD7
Bit 7
enters the SGFMCLKD divider.
0
Figure 10-5. SGFM Test Register (SGFMTST)
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Register.
= Reserved
RSVD6
6
0
RSVD5
5
0
RSVD4
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
4
0
3
0
0
10.8.3.1 Setting the
2
0
0
RSVD1
1
0
MOTOROLA
RSVD0
Bit 0
0