MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 152
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Reset Controller Module
5.7.3 Concurrent Resets
5.7.3.1 Reset Flow
5.7.3.2 Reset Status Flags
Advance Information
152
This section describes the concurrent resets. As in the previous
discussion references in parentheses refer to the state numbers in
Figure
If a power-on reset or low-voltage detect condition is detected during any
reset sequence, the reset sequence starts immediately (0).
If the external RESET pin is asserted for at least four rising CLKOUT
edges while waiting for PLL lock or the 512 cycles, the external reset is
recognized. Reset processing switches to wait for the external RESET
pin to negate (8).
If a loss of clock or loss of lock condition is detected while waiting for the
current bus cycle to complete (5, 6) for an external reset request, the
cycle is terminated. The reset status bits are latched (7) and reset
processing waits for the external RESET pin to negate (8).
If a loss of clock or loss of lock condition is detected during the 512 cycle
wait, the reset sequence continues after a PLL lock (9, 9A).
For a POR reset, the POR and LVD bits in the RSR register are set, and
the SOFT, WDR, EXT, LOC, and LOL bits are cleared even if another
type of reset condition is detected during the reset sequence for the
POR.
If a loss of clock or loss of lock condition is detected while waiting for the
current bus cycle to complete (5, 6) for an external reset request, the
EXT, SOFT, and/or WDR bits along with the LOC and/or LOL bits are
set.
If the RSR bits are latched (7) during the EXT, SOFT, and/or WDR reset
sequence with no other reset conditions detected, only the EXT, SOFT,
and/or WDR bits are set.
Freescale Semiconductor, Inc.
For More Information On This Product,
5-4.
Go to: www.freescale.com
Reset Controller Module
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
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