MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 602
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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JTAG Test Access Port and OnCE
22.14.11 Enabling OnCE Memory Breakpoints
22.14.12 Pipeline Information and Write-Back Bus Register
Advance Information
602
When the OnCE memory breakpoint mechanism is enabled with a
breakpoint counter value of zero, the device enters debug mode after
completing the execution of the instruction that caused the memory
breakpoint to occur. In case of breakpoints on instruction fetches, the
breakpoint is acknowledged immediately after the execution of the
fetched instruction. In case of breakpoints on data memory addresses,
the breakpoint is acknowledged after the completion of the memory
access instruction.
A number of on-chip registers store the CPU pipeline status and are
configured in the CPU Scan Chain Register (CPUSCR) for access by the
OnCE controller. The CPUSCR is used to restore the pipeline and
resume normal device activity upon return from debug mode. The
CPUSCR also provides a mechanism for the emulator software to
access processor and memory contents.
diagram of the pipeline information registers contained in the CPUSCR.
Freescale Semiconductor, Inc.
For More Information On This Product,
TDI
Figure 22-14. CPU Scan Chain Register (CPUSCR)
JTAG Test Access Port and OnCE
Go to: www.freescale.com
15
31
31
31
CTL
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
0
WBBR
PSR
PC
15
Figure 22-14
IR
0
0
0
shows the block
0
TDO
MOTOROLA
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