MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 330

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Timer Modules (TIM1 and TIM2)
16.7.7 Timer Toggle-On-Overflow Register
Advance Information
330
Address: TIM1 — 0x00ce_0008
Reset:
Read: Anytime
Write: Anytime
TOV[3:0]— Toggle-On-Overflow Bits
Read:
Write:
Figure 16-10. Timer Toggle-On-Overflow Register (TIMTOV)
TOV[3:0] toggles the output compare pin on overflow. This feature
only takes effect when in output compare mode. When set, it takes
precedence over forced output compare but not channel 3 override
events.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Toggle output compare pin on overflow feature enabled
0 = Toggle output compare pin on overflow feature disabled
TIM2 — 0x00cf_0008
WRITE TIMCx REGISTERS
Bit 7
READ TIMCx REGISTERS
0
0
Timer Modules (TIM1 and TIM2)
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= Writes have no effect and the access terminates without a transfer error exception.
6
0
0
Figure 16-9. Fast Clear Flag Logic
TFFCA
CxF
WRITE TIMFLG1 REGISTER
5
0
0
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
4
0
0
DATA BIT x
TOV3
3
0
TOV2
2
0
TOV1
CLEAR
CxF FLAG
1
0
MOTOROLA
TOV0
Bit 0
0