MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 561
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
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22.2 Introduction
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
22.14.12.3 Control State Register . . . . . . . . . . . . . . . . . . . . . . . . . . 603
22.14.12.4 Writeback Bus Register . . . . . . . . . . . . . . . . . . . . . . . . . 605
22.14.12.5 Processor Status Register . . . . . . . . . . . . . . . . . . . . . . .605
22.14.13 Instruction Address FIFO Buffer (PC FIFO) . . . . . . . . . . . . 606
22.14.14 Reserved Test Control Registers . . . . . . . . . . . . . . . . . . . . 607
22.14.15 Serial Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
22.14.16 OnCE Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
22.14.17 Target Site Debug System Requirements . . . . . . . . . . . . . 608
22.14.18 Interface Connector for JTAG/OnCE Serial Port . . . . . . . . 608
The MMC2114, MMC2113, and MMC2112 have two JTAG (Joint Test
Action Group) TAP (test access port) controllers:
At power-up, only the top-level TAP controller will be visible. If desired,
a user can then enable the low-level OnCE controller which will in turn
disable the top-level TAP controller. The top-level TAP controller will
remain disabled until either power is removed and reapplied or until the
test reset signal, TRST, is asserted (logic 0).
The OnCE TAP controller can be enabled in either of two ways:
Refer to
1. A top-level controller that allows access to the Boundary Scan
2. A low-level OnCE (on-chip emulation) controller that allows
1. With the top-level TAP controller in its test-logic-reset state:
2. Shift the ENABLE_MCU_ONCE instruction, 0x3, into the top-level
Freescale Semiconductor, Inc.
For More Information On This Product,
(external pins) Register, IDCODE Register, and Bypass Register
access to the central processor unit (CPU) and debugger-related
registers
TAP controller’s Instruction Register (IR) and pass through the
TAP controller state update-IR.
a. Deassert TRST, test reset (logic1)
b. Assert DE, the debug event (logic 0) for two TCLK, test clock,
Figure
JTAG Test Access Port and OnCE
cycles
Go to: www.freescale.com
22-1.
JTAG Test Access Port and OnCE
Advance Information
Introduction
561
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