MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 382

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Serial Communications Interface Modules (SCI1 and SCI2)
17.12.3 Data Sampling
Advance Information
382
RT CLOCK COUNT
RESET RT CLOCK
RT CLOCK
SAMPLES
RXD
1
1
1
Serial Communications Interface Modules (SCI1 and SCI2)
After an entire frame shifts into the receive shift register, the data portion
of the frame transfers to SCIDRH and SCIDRL. The RDRF flag is set,
indicating that the received data can be read. If the RIE bit is also set,
RDRF generates an interrupt request.
The receiver samples the RXD pin at the RT clock rate. The RT clock is
an internal signal with a frequency 16 times the baud rate. To adjust for
baud rate mismatch, the RT clock resynchronizes:
To locate the start bit, data recovery logic does an asynchronous search
for a 0 preceded by three 1s. When the falling edge of a possible start bit
occurs, the RT clock begins to count to 16.
1
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Freescale Semiconductor, Inc.
Figure 17-16. Receiver Data Sampling
1
For More Information On This Product,
After every start bit
After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)
QUALIFICATION
1
START BIT
1
1
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0
0
VERIFICATION
START BIT
0
0
START BIT
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
SAMPLING
0
DATA
0
0
MOTOROLA
LSB