MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 651
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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A.4.2 Disabled OnCE Access
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
When FLASH security is enabled, the MCU will boot only in single-chip
mode and will fetch its reset vector from address 0x0000_0000 of the
on-chip FLASH.
This security affords protection only to applications in which the MCU
operates in single-chip mode. Operating in any other mode would make
the external bus interface (EBI) available and would be inherently
insecure.
When security is enabled, any attempt to override the default single-chip
operating mode by asserting the reset configuration (RCON) pin in
conjunction with mode select inputs D26, D17, and D16 will be ignored.
When security is enabled, override will be allowed only for the RPLLSEL,
RPLLREF, and RLOAD bits in the RCON register. These bits are
overridden by asserting RCON in conjunction with appropriate logic
levels applied to the D[23:22] pins (RPLLSEL and RPLLREF) and the
D21 pin (RLOAD). The override inputs for all other RCON bits will be
ignored.
On-chip FLASH can be read by issuing commands across the OnCE
port which is the debug interface for the M•CORE CPU. The TRST,
TCLK, TMS, TDO, and TDI pins comprise a JTAG (Joint Test Action
Group) interface onto which the OnCE port functionality is mapped.
When the MCU boots, the top level JTAG TAP (test access port) is active
and provides the chip’s boundary scan capability and access to its ID
register.
OnCE port features are enabled by:
Proper implementation of FLASH security requires that no access to the
OnCE port is provided when security is enabled. OnCE port access is
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
Asserting the debug enable (DE) input for two TCLK periods when
TRST is negated
Shifting the ENABLE_MCU_ONCE command into the TAP
controller’s instruction register (IR), entering the UPDATE_IR
state and returning to the RUN_TEST/IDLE state.
Go to: www.freescale.com
Security
Advance Information
Security
651
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