MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 458

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Queued Analog-to-Digital Converter (QADC)
Advance Information
458
QS[9:6] — Queue Status Field
TOR2 is set when a trigger event is received while queue 2 is
executing, suspended, or a trigger is pending. TOR2 has no effect on
queue execution. A trigger event that causes a trigger overrun is not
retained since it is considered unexpected. An unexpected trigger
event may be a system overrun situation.
Once set, TOR2 is cleared only by a reset or by writing a 0 to it.
The 4-bit read-only QS field indicates the current condition of queue 1
and queue 2. The five queue status conditions are:
The two most significant bits are associated primarily with queue 1,
and the remaining two bits are associated with queue 2. Because the
priority scheme between the two queues causes the status to be
interlinked, the status bits must be considered as one 4-bit field.
Table 19-7
status of queue 1 and queue 2.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
1 = At least one unexpected queue 2 trigger event has occurred.
0 = No unexpected queue 2 trigger events have occurred.
– Idle
– Active
– Paused
– Suspended
– Trigger pending
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QS[9:6]
shows the bits in the QS field and how they denote the
0000
0001
0010
0011
0100
0101
0110
Table 19-7. Queue Status
Queue 1 idle, queue 2 idle
Queue 1 idle, queue 2 paused
Queue 1 idle, queue 2 active
Queue 1 idle, queue 2 trigger pending
Queue 1 paused, queue 2 idle
Queue 1 paused, queue 2 paused
Queue 1 paused, queue 2 active
Queue 1/Queue 2 States
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA