MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 451
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
RESUME — Queue 2 Resume Bit
BQ2[6:0] — Beginning of Queue 2 Field
RESUME selects the resumption point for queue 2 after its operation
is suspended due to a queue 1 trigger event. If RESUME is changed
during the execution of queue 2, the change is not recognized until an
end-of-queue condition is reached or the operating mode of queue 2
is changed.
The primary reason for selecting re-execution of the entire queue or
subqueue is to guarantee that all samples are taken consecutively in
one scan (coherency).
When subqueues are not used, queue 2 execution restarts after
suspension with the first CCW in queue 2. When a pause has
previously occurred in queue 2 execution, queue execution restarts
after suspension with the first CCW in the current subqueue.
A subqueue is considered to be a stand-alone sequence of
conversions. Once a pause flag has been set to report subqueue
completion, that subqueue is not repeated until all CCWs in queue 2
are executed.
An example of using the RESUME bit is when the frequency of
queue 1 trigger events prohibit queue 2 completion. If the rate of
queue 1 execution is too high, it is best for queue 2 execution to
continue with the CCW that was being converted when queue 2 was
suspended. This allows queue 2 to eventually complete execution.
BQ2[6:0] denotes the CCW location where queue 2 begins. This
allows the length of queue 1 and queue 2 to vary. The BQ2 field also
serves as an end-of-queue condition for queue 1.
The beginning of queue 2 is defined by programming the BQ2 field in
QACR2. BQ2 is usually set before or at the same time as the queue
operating mode for queue 2 is selected. If BQ2[6:0] 64, queue 2 has
no entries, the entire CCW table is dedicated to queue 1, and CCW63
is the end-of-queue 1. If BQ2[6:0] is 0, the entire CCW table is
dedicated to queue 2. A special case occurs when an operating mode
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
1 = After suspension, begin execution with the aborted CCW in
0 = After suspension, begin execution with the first CCW of
queue 2.
queue 2 or the current subqueue of queue 2.
Go to: www.freescale.com
Queued Analog-to-Digital Converter (QADC)
Register Descriptions
Advance Information
451
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