MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 365
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
NOTE:
Serial Communications Interface Modules (SCI1 and SCI2)
TE — Transmitter Enable Bit
RE — Receiver Enable Bit
When LOOPS = 0 and TE = RE = 1, the RXD pin is an input and the
TXD pin is an output regardless of the state of the DDRSC1 (TXD) and
DDRSC0 (RXD) bits.
RWU — Receiver Wakeup Bit
SBK — Send Break Bit
This read/write bit enables the transmitter and configures the TXD pin
as the transmitter output. Toggling TE queues an idle frame. Reset
clears TE.
This read/write bit enables the receiver. Reset clears RE.
This read/write bit puts the receiver in a standby state that inhibits
receiver interrupt requests. The WAKE bit determines whether an idle
input or an address mark wakes up the receiver and clears RWU.
Reset clears RWU.
Setting this read/write bit causes the SCI to send break frames of 10
(M = 0) or 11 (M =1) logic 0s. To send one break frame, set SBK and
then clear it before the break frame is finished transmitting. As long as
SBK is set, the transmitter continues to send break frames.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Transmitter enabled
0 = Transmitter disabled
1 = Receiver enabled
0 = Receiver disabled
1 = Receiver asleep when RE = 1
0 = Receiver awake when RE = 1
1 = Transmitter sends break frames.
0 = Transmitter does not send break frames.
Go to: www.freescale.com
Serial Communications Interface Modules (SCI1 and SCI2)
Memory Map and Registers
Advance Information
365
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