MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 513
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
A time separator is provided between the triggers and the end of
conversion (EOC). The relationship to QCLK displayed is not
guaranteed.
CWPQ1 and CWPQ2 typically lag CWP and only match CWP when the
associated queue is inactive. Another way to view CWPQ1 and CWPQ2
is that these registers update when EOC triggers the write to the result
register.
For the CCW with the pause bit set (CCW0), CWP does not increment
until triggered. For the CCW with the pause bit clear (CCW1), the CWP
increments with the EOC.
The conversion results Q1 RESx show the result associated with CCWx,
such that R0 represents the result associated with CCW0.
Figure 19-47
single-scan with same assumptions in example 1 except:
When the gate closes and opens again, the conversions start with the
first CCW in Q1.
When the gate closes, the active conversion completes before the
queue goes idle.
When Q1 completes, both the CF1 bit sets and the SSE bit clears.
In this mode, the PF1 bit sets to reflect that a gate closing occurred
before the queue completed.
Figure 19-48
continuous scan mode with the same assumptions as in
At the end of Q1,the completion flag CF1 sets and the queue restarts. If
the queue starts a second time and completes, the trigger overrun flag
TOR1 sets.
•
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
No pause bits set in any CCW
Externally gated single scan mode for Q1
Single scan enable bit (SSE1) is set.
Go to: www.freescale.com
shows the timing for conversions in externally gated
shows the timing for conversions in externally gated
Queued Analog-to-Digital Converter (QADC)
Pin Connection Considerations
Advance Information
Figure
19-47.
513
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