MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 459

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
One or both queues may be in the idle state. When a queue is idle,
CCWs are not being executed for that queue, the queue is not in the
pause state, and no trigger is pending.
The idle state occurs when a queue is disabled, when a queue is in a
reserved mode, or when a queue is in a valid queue operating mode
awaiting a trigger event to initiate queue execution.
A queue is in the active state when a valid queue operating mode is
selected, when the selected trigger event has occurred, or when the
QADC is performing a conversion specified by a CCW from that
queue.
Only one queue can be active at a time. One or both queues can be
in the paused state. A queue is paused when the previous CCW
executed from that queue had the pause bit set. The QADC does not
execute any CCWs from the paused queue until a trigger event
occurs. Consequently, the QADC can service queue 2 while queue 1
is paused.
Only queue 2 can be in the suspended state. When a trigger event
occurs on queue 1 while queue 2 is executing, the current queue 2
conversion is aborted. The queue 2 status is reported as suspended.
Queue 2 transitions back to the active state when queue 1 becomes
idle or paused.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Go to: www.freescale.com
QS[9:6]
1000
1001
1010
1011
1100
1101
0111
1110
1111
Table 19-7. Queue Status (Continued)
Queue 1 paused, queue 2 trigger pending
Queue 1 active, queue 2 idle
Queue 1 active, queue 2 paused
Queue 1 active, queue 2 suspended
Queue 1 active, queue 2 trigger pending
Reserved
Reserved
Reserved
Reserved
Queue 1/Queue 2 States
Queued Analog-to-Digital Converter (QADC)
Register Descriptions
Advance Information
459