MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 193
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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8.8.3 Autovectored and Vectored Interrupt Requests
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
If an interrupt is pending at a given priority level and both the
corresponding FIER and NIER bits are set, then both the corresponding
FIPR and NIPR bits are set, assuming these bits are not masked.
Fast interrupt requests always have priority over normal interrupt
requests, even if the normal interrupt request is at a higher priority level
than the highest fast interrupt request.
If the fast interrupt signal is asserted when the normal interrupt signal is
already asserted, then the normal interrupt signal is negated.
IPR, NIPR, and FIPR are read-only. To clear a pending interrupt, the
interrupt must be cleared at the source using a special clearing
sequence defined by each source. All interrupt sources to the interrupt
controller are to be held until recognized and cleared by the interrupt
service routine. The interrupt controller does not have any edge-detect
logic. Edge-triggered interrupt sources are handled at the source
module.
In ICR, the MASK[4:0] bits can mask interrupt sources at and below a
selected priority level. The MFI bit determines whether the mask applies
only to normal interrupts or to fast interrupts with all normal interrupts
being masked. The ME bit enables interrupt masking.
ISR reflects the current vector number and the states of the signals to
the CPU.
The vector number and fast/normal interrupt sources are synchronized
before being sent to the CPU. Thus, the interrupt controller adds one
clock of latency to the interrupt sequence. The fast and normal interrupt
raw sources are not synchronized and are used to wake up the CPU
during stop mode.
The AE bit in ICR enables autovectored interrupt requests to the CPU.
AE is set by default, and all interrupt requests are autovectored. An
interrupt handler may read FIPR or NIPR to determine the priority of the
interrupt source. If multiple interrupt sources share the same priority
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Interrupt Controller Module
Interrupt Controller Module
Functional Description
Advance Information
193
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