MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 603
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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22.14.12.1 Program Counter Register
22.14.12.2 Instruction Register
22.14.12.3 Control State Register
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
The Program Counter Register (PC) is a 32-bit latch that stores the value
in the CPU program counter when the device enters debug mode. The
CPU PC is affected by operations performed during debug mode and
must be restored by the external command controller when the CPU
returns to normal mode.
The Instruction Register (IR) provides a mechanism for controlling the
debug session. The IR allows the debug control block to execute
selected instructions; the debug control module provides single-step
capability.
When scan-out begins, the IR contains the opcode of the next instruction
to be executed at the time debug mode was entered. This opcode must
be saved in order to resume normal execution at the point debug mode
was entered.
On scan-in, the IR can be filled with an opcode selected by debug control
software in preparation for exiting debug mode. Selecting appropriate
instructions allows a user to examine or change memory locations and
processor registers.
Once the debug session is complete and normal processing is to be
resumed, the IR can be loaded with the value originally scanned out.
The Control State Register (CTL) is used to set control values when
debug mode is exited. On scan-in, this register is used to control specific
aspects of the CPU. Certain bits reflect internal processor status and
should be restored to their original values.
The CTL register is a 16-bit latch that stores the value of certain internal
CPU state variables before debug mode is entered. This register is
affected by the operations performed during the debug session and
should be restored by the external command controller when returning
to normal mode. In addition to saved internal state variables, the bits are
used by emulation firmware to control the debug process.
Freescale Semiconductor, Inc.
For More Information On This Product,
JTAG Test Access Port and OnCE
Go to: www.freescale.com
JTAG Test Access Port and OnCE
Functional Description
Advance Information
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