MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 367
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
NOTE:
Serial Communications Interface Modules (SCI1 and SCI2)
RDRF — Receive Data Register Full Flag
IDLE — Idle Line Flag
When RWU of SCICR2 =1, an idle line condition does not set the IDLE
flag.
OR — Overrun Flag
The RDRF flag is set when the data in the receive shift register is
transferred to SCIDRH and SCIDRL. It signals that the received data
is available to the MCU. If the RIE bit is set in SCICR2, RDRF
generates an interrupt request. Clear RDRF by reading the SCISR1
and then reading SCIDRL. Reset clears RDRF.
The IDLE flag is set when 10 (if M = 0) or 11 (if M = 1) consecutive
logic 1s appear on the receiver input. If the ILIE bit in SCICR2 is set,
IDLE generates an interrupt request. Once IDLE is cleared, a valid
frame must again set the RDRF flag before an idle condition can set
the IDLE flag. Clear IDLE by reading SCISR1 and then reading
SCIDRL. Reset clears IDLE.
The OR flag is set if data is not read from SCIDRL before the receive
shift register receives the stop bit of the next frame. This is a receiver
overrun condition. If the RIE bit in SCICR2 is set, OR generates an
interrupt request. The data in the shift register is lost, but the data
already in the SCIDRH and SCIDRL is not affected. Clear OR by
reading SCISR1 and then reading SCIDRL. Reset clears OR.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Received data available in SCIDRH and SCIDRL
0 = Received data not available in SCIDRH and SCIDRL
1 = Receiver idle
0 = Receiver active or idle since reset or idle since IDLE flag last
1 = Overrun
0 = No overrun
cleared
Go to: www.freescale.com
Serial Communications Interface Modules (SCI1 and SCI2)
Memory Map and Registers
Advance Information
367
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