MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 581
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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22.13 Signal Descriptions
22.13.1 Debug Serial Input (TDI)
22.13.2 Debug Serial Clock (TCLK)
22.13.3 Debug Serial Output (TDO)
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
NOTE:
The OnCE pin interface is used to transfer OnCE instructions and data
to the OnCE control block. Depending on the particular resource being
accessed, the CPU may need to be placed in debug mode. For
resources outside of the CPU block and contained in the OnCE block,
the processor is not disturbed and may continue execution. If a
processor resource is required, the OnCE controller may assert an
internal debug request (DBGRQ) to the CPU. This causes the CPU to
finish the instruction being executed, save the instruction pipeline
information, enter debug mode, and wait for further commands.
Asserting DBGRQ causes the device to exit stop, doze, or wait mode
and to enter debug mode.
Data and commands are provided to the OnCE controller through the
TDI pin. Data is latched on the rising edge of the TCLK serial clock. Data
is shifted into the OnCE serial port least significant bit (LSB) first.
The TCLK pin supplies the serial clock to the OnCE control block. The
serial clock provides pulses required to shift data and commands into
and out of the OnCE serial port. (Data is clocked into the OnCE on the
rising edge and is clocked out of the OnCE serial port on the falling
edge.) The debug serial clock frequency must be no greater than
50 percent of the processor clock frequency.
Serial data is read from the OnCE block through the TDO pin. Data is
always shifted out the OnCE serial port LSB first. Data is clocked out of
the OnCE serial port on the falling edge of TCLK. TDO is three-stateable
and is actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCLK.
Freescale Semiconductor, Inc.
For More Information On This Product,
JTAG Test Access Port and OnCE
Go to: www.freescale.com
JTAG Test Access Port and OnCE
Advance Information
Signal Descriptions
581
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