MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 506
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Queued Analog-to-Digital Converter (QADC)
Advance Information
506
To prepare the QADC for a scan sequence, write to the CCW table to
specify the desired channel conversions. The criteria for queue
execution is established by selecting the queue operating mode. The
queue operating mode determines what type of trigger event starts
queue execution. A trigger event refers to any of the ways that cause the
QADC to begin executing the CCWs in a queue or subqueue. An
external trigger is only one of the possible trigger events.
A scan sequence may be initiated by:
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Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
A software command
Expiration of the periodic/interval timer
An external trigger signal
An external gated signal (queue 1 only)
CONVERSION COMMAND
P — PAUSE AFTER CONVERSION
BYP — BYPASS BUFFER AMPLIFIER
IST — INPUT SAMPLE TIME
CHAN — CHANNEL NUMBER AND
BEGINNING OF QUEUE 1
BEGINNING OF QUEUE 2
P
9
WORD (CCW) TABLE
Figure 19-43. QADC Conversion Queue Operation
END OF QUEUE 1
END OF QUEUE 2
10-BIT CONVERSION COMMAND
UNTIL NEXT TRIGGER
BYP
8
Go to: www.freescale.com
END-OF-QUEUE CODE
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WORD FORMAT
[7:6]
IST
CHAN
[5:0]
CHANNEL SELECT,
A/D CONVERSION
SAMPLE, HOLD,
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
15 14 13 12 11 10
0
S
RIGHT-JUSTIFIED, UNSIGNED RESULT
LEFT-JUSTIFIED, UNSIGNED RESULT
0 0 0 0 0
LEFT-JUSTIFIED, SIGNED RESULT
10-BIT RESULT, READABLE IN
RESULT
[15:6]
[15:6]
THREE 16-BIT FORMATS
RESULT
RESULT WORD TABLE
0
0
RESULT
0 0 0 0 0
0 0 0 0 0
[9:0]
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[5:0]
[5:0]
MOTOROLA
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