D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 1121

IC H8S/2300 MCU ROMLESS 128QFP

D12321VF25V

Manufacturer Part Number
D12321VF25V
Description
IC H8S/2300 MCU ROMLESS 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of D12321VF25V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
86
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
D12321VF25V
Manufacturer:
Renesas
Quantity:
675
Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
TIOR4—Timer I/O Control Register 4
Bit
Initial value
Read/Write
:
:
:
TGR4B I/O Control
0
1
IOB3
R/W
7
0
0
1
0
1
0
1
0
1
0
1
*
IOB2
R/W
6
0
0
1
0
1
0
1
0
1
0
1
*
*
TGR4B
is output
compare
register
TGR4B
is input
capture
register
IOB1
R/W
5
0
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCB
Capture input
source is TGR3C
compare match/
input capture
IOB0
R/W
4
0
4
0
1
TGR4A I/O Control
pin
0
1
0
1
IOA3
R/W
3
0
0
1
0
1
0
1
*
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of
TGR3C compare match/input
capture
0
1
0
1
0
1
0
1
0
1
*
*
IOA2
TGR4A
is output
compare
register
TGR4A
is input
capture
register
R/W
2
0
Rev.6.00 Sep. 27, 2007 Page 1089 of 1268
H'FE92
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
IOA1
Capture input
source is
TIOCA
Capture input
source is TGR3A
compare match/
input capture
R/W
1
0
* : Don’t care
Appendix B Internal I/O Registers
4
pin
IOA0
R/W
0
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of
TGR3A compare match/input
capture
REJ09B0220-0600
* : Don’t care
TPU4

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