D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 224

• Manufacturer Part Number: D12321VF25V
• Description: IC H8S/2300 MCU ROMLESS 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12321VF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Bus Controller
6.5.10
With DRAM, in addition to full access (normal access) in which data is accessed by outputting a
row address for each access, a fast page mode is also provided which can be used when making a
number of consecutive accesses to the same row address. This mode enables fast (burst) access of
data by simply changing the column address after the row address has been output. Burst access
can be selected by setting the BE bit in MCR to 1.
Burst Access (Fast Page Mode) Operation Timing: Figure 6.20 shows the operation timing for
burst access. When there are consecutive access cycles for DRAM space, the CAS signal and
column address output cycles (two states) continue as long as the row address is the same for
consecutive access cycles. The row address used for the comparison is set with bits MXC1 and
MXC0 in MCR.
The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion
method and timing are the same as for full access. For details, see section 6.5.8, Wait Control.
Rev.6.00 Sep. 27, 2007 Page 192 of 1268
REJ09B0220-0600
Read
Write
Note: n = 2 to 5
Burst Operation
CAS, LCAS
CSn (RAS)
HWR (WE)
HWR ( WE)
D
D
A
15
15
23
to D
to D
to A
Figure 6.20 Operation Timing in Fast Page Mode
φ
0
0
0
T
p
Row
T
r
T
c1
Column 1
T
c2
T
c1
Column 2
T
c2