D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 386

IC H8S/2300 MCU ROMLESS 128QFP

D12321VF25V

Manufacturer Part Number
D12321VF25V
Description
IC H8S/2300 MCU ROMLESS 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of D12321VF25V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
86
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
D12321VF25V
Manufacturer:
Renesas
Quantity:
675
Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 I/O Ports
Port 1 Data Register (P1DR)
P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P1
P1DR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
Port 1 Register (PORT1)
Note: * Determined by state of pins P1
PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port 1 pins (P1
If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1
read is performed while P1DDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORT1 contents are determined by the pin states, as
P1DDR and P1DR are initialized. PORT1 retains its prior state in software standby mode.
Rev.6.00 Sep. 27, 2007 Page 354 of 1268
REJ09B0220-0600
Bit
Initial value :
R/W
Bit
Initial value :
R/W
:
:
:
:
P17DR
R/W
P17
— *
R
7
0
7
P16DR
R/W
P16
— *
R
6
0
6
7
to P1
7
P15DR
to P1
R/W
P15
— *
0
R
) must always be performed on P1DR.
5
0
5
0
.
P14DR
R/W
P14
— *
R
4
0
4
P13DR
R/W
P13
— *
R
3
0
3
P12DR
R/W
P12
— *
R
2
0
2
P11DR
R/W
P11
— *
R
1
0
1
7
to P1
P10DR
R/W
P10
— *
R
0
0
0
0
).

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