D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 218

• Manufacturer Part Number: D12321VF25V
• Description: IC H8S/2300 MCU ROMLESS 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12321VF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Bus Controller
6.5.6
Figure 6.15 shows the basic access timing for DRAM space. The basic DRAM access timing is 4
states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or
disabling of wait insertion, and do not affect the number of access states. When the corresponding
bit in ASTCR is cleared to 0, wait states cannot be inserted in the DRAM access cycle.
The 4 states of the basic timing consist of one T
output cycle), and two T
Rev.6.00 Sep. 27, 2007 Page 186 of 1268
REJ09B0220-0600
Note: n = 2 to 5
Read
Write
Basic Timing
CAS, LCAS
CSn (RAS)
HWR (WE)
HWR (WE)
D
D
A
15
15
23
to D
to D
to A
c
φ
0
0
0
(column address output cycle) states, T
Figure 6.15 Basic Access Timing
T
p
p
(precharge cycle) state, one T
Row
T
r
T
c1
c1
and T
Column
c2
.
T
r
c2
(row address