D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 173

• Manufacturer Part Number: D12321VF25V
• Description: IC H8S/2300 MCU ROMLESS 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12321VF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 5 Interrupt Controller
5.6.3
Operation
The interrupt controller has three main functions in DTC and DMAC * control.
Selection of Interrupt Source: With the DMAC * , the activation source is input directly to each
channel. The activation source for each DMAC * channel is selected with bits DTF3 to DTF0 in
DMACR. Whether the selected activation source is to be managed by the DMAC * can be selected
with the DTA bit of DMABCR. When the DTA bit is set to 1, the interrupt source constituting that
DMAC * activation source is not a DTC activation source or CPU interrupt source.
For interrupt sources other than interrupts managed by the DMAC * , it is possible to select DTC
activation request or CPU interrupt request with the DTCE bit of DTCERA to DTCERF in the
DTC.
After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the
CPU in accordance with the specification of the DISEL bit of MRB in the DTC.
When the DTC has performed the specified number of data transfers and the transfer counter value
is zero, the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU after the DTC data
transfer.
Determination of Priority: The DTC activation source is selected in accordance with the default
priority order, and is not affected by mask or priority levels. See section 7.6, Interrupts, and
section 8.3.3, DTC Vector Table, for the respective priorities.
With the DMAC * , the activation source is input directly to each channel.
Operation Order: If the same interrupt is selected as a DTC activation source and a CPU
interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception
handling.
If the same interrupt is selected as a DMAC * activation source and a DTC activation source or
CPU interrupt source, operations are performed for them independently according to their
respective operating statuses and bus mastership priorities.
Table 5.11 summarizes interrupt source selection and interrupt source clearance control according
to the settings of the DTA bit of DMABCR in the DMAC * , the DTCE bit of DTCERA to
DTCERF in the DTC, and the DISEL bit of MRB in the DTC.
Note: * The DMAC is not supported in the H8S/2321.
Rev.6.00 Sep. 27, 2007 Page 141 of 1268
REJ09B0220-0600